Generate production-ready VHDL register modules from VHDL annotations, YAML, XML, or JSON. Built-in CDC synchronizers, subregisters, and comprehensive documentation output.
pip install axion-hdl
$ axion-hdl -s spi_master.yaml -o output/ --all
# Generated files:
✓ spi_master_axion_reg.vhd AXI4-Lite slave
✓ spi_master_regs.h C header
✓ spi_master_regs.xml IP-XACT
✓ spi_master_regs.yaml YAML map
✓ register_map.md Documentation
→ All files generated successfully!From simple LED controllers to complex SoC peripherals — Axion-HDL handles it all.
Define registers in VHDL comments, YAML, XML, or JSON. Use whatever fits your workflow.
Built-in 2/3/4-stage clock domain crossing. Safe register access across clock domains.
Pack multiple bit fields into a single address. Perfect for status/control registers.
Automatically split 64-bit+ signals across multiple addresses. No manual splitting needed.
Generate pulse signals for register access. Ideal for FIFOs and interrupt handlers.
Auto-generate Markdown docs, C headers, and IP-XACT XML for every register map.
Three simple steps from definition to integration.
Use VHDL annotations or create a YAML/XML/JSON file describing your register map.
-- VHDL annotation
signal status : std_logic_vector(31 downto 0); -- @axion RO
signal control : std_logic_vector(31 downto 0); -- @axion RWA single command generates all output files — VHDL, headers, and documentation.
$ axion-hdl -s my_module.vhd -o output/ --allInstantiate the generated module in your design. Connect AXI bus and register signals.
regs : entity work.my_module_axion_reg
port map (
-- AXI4-Lite bus
axi_aclk => clk,
axi_aresetn => rst_n,
axi_awaddr => s_axi_awaddr,
axi_awvalid => s_axi_awvalid,
axi_awready => s_axi_awready,
-- ... other AXI signals
-- Register signals
status => status_sig,
control => control_reg
);Choose the format that fits your workflow. All produce identical output.
module: spi_master
base_addr: "0x0000"
config:
cdc_en: true
registers:
- name: control
addr: "0x00"
access: RW
w_strobe: true
description: "SPI control register"
- name: status
addr: "0x04"
access: RO
r_strobe: true
description: "SPI status (clears on read)"-- @axion_def BASE_ADDR=0x0000 CDC_EN
architecture rtl of spi_master is
-- Control register
signal control : std_logic_vector(31 downto 0);
-- @axion RW W_STROBE DESC="SPI control register"
-- Status register
signal status : std_logic_vector(31 downto 0);
-- @axion RO R_STROBE DESC="SPI status (clears on read)"
begin
...
end architecture rtl;<?xml version="1.0" encoding="UTF-8"?>
<register_map module="spi_master" base_addr="0x0000">
<config cdc_en="true"/>
<register name="control" addr="0x00"
access="RW" w_strobe="true"
description="SPI control register"/>
<register name="status" addr="0x04"
access="RO" r_strobe="true"
description="SPI status (clears on read)"/>
</register_map>{
"module": "spi_master",
"base_addr": "0x0000",
"config": {
"cdc_en": true
},
"registers": [
{
"name": "control",
"addr": "0x00",
"access": "RW",
"w_strobe": true,
"description": "SPI control register"
},
{
"name": "status",
"addr": "0x04",
"access": "RO",
"r_strobe": true,
"description": "SPI status (clears on read)"
}
]
}Pick the interface that suits your workflow best.
Perfect for scripts and CI/CD pipelines. Fast, scriptable, and easy to integrate.
axion-hdl -s src/ -o output/ --all
Full programmatic control for custom workflows and tool integration.
from axion_hdl import AxionHDL
Interactive visual editor for register maps. Great for exploration and prototyping.
pip install axion-hdl[gui]