Automate AXI register generation for FPGA and ASIC. Create AXI4-Lite register interfaces from VHDL annotations, YAML, XML, JSON, or TOML. Built-in CDC synchronizers, subregisters, and complete documentation.
pip install axion-hdl
Pick the interface that suits your workflow best.
Perfect for scripts and CI/CD pipelines. Fast, scriptable, and easy to integrate.
axion-hdl -s src/ -o output/ --all
Full programmatic control for custom workflows and tool integration.
from axion_hdl import AxionHDL
Interactive visual editor for register maps. Great for exploration and quick local prototyping.
pip install axion-hdl[gui]
axion-hdl --gui
Drop in a register definition and generate VHDL/SystemVerilog register spaces and C headers in seconds.
Runs the actual axion-hdl engine on the server.
Click "Generate" to run axion-hdl...Generated VHDL will appear here...Generated SystemVerilog will appear here...Generated C header will appear here...From simple LED controllers to complex SoC peripherals.
Parse annotations from .vhd or .sv files. Generate AXI4-Lite register interfaces in VHDL, SystemVerilog, or both — plus C headers for drivers.
Define registers in VHDL/SV annotations, YAML, XML, JSON, or TOML. Use whatever fits your workflow.
Built-in 2/3/4-stage clock domain crossing. Safe register access across clock domains with zero boilerplate.
Pack bit fields into a single address. Automatically split 64-bit+ signals across multiple registers — no manual work needed.
Auto-generate Markdown docs, C headers, and IP-XACT XML. Enumerated values propagate into all outputs automatically.
Compose nested register maps from multiple source files into one unified AXI4-Lite address space.