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Why use a register generator?
If you've ever designed an FPGA or ASIC with a processor interface, you know the drill: write the AXI4-Lite slave by hand, keep the C header in sync with the HDL, update the documentation every time an address moves. It's tedious and error-prone.
Register generators solve this by letting you define the register map once and automatically producing:
- HDL code (VHDL and/or SystemVerilog) for the AXI4-Lite slave
- C/C++ headers with register addresses and bit-field macros
- Documentation (HTML, Markdown, PDF)
- IP-XACT XML for EDA tool import
The tools in this comparison cover the full spectrum — from a $199/year SaaS product to research-lab tools that haven't seen a commit since 2019.
Quick comparison table
| Tool | Price | VHDL out | SV out | VHDL/SV in | GUI | Open source | Active |
|---|---|---|---|---|---|---|---|
| Axion-HDL | Free | ✓ | ✓ | ✓ both | ✓ | ✓ | ✓ |
| airhdl | $199/yr | ✓ | ✓ | ✗ | ✓ | ✗ | ✓ |
| hdl-registers | Free | ✓ | ✓ | ✗ | ✗ | ✓ | ✓ |
| vhdmmio | Free | ✓ | ✗ | ✗ | ✗ | ✓ | ✗ (2019) |
| RgGen | Free | ✓ | ✓ | ✗ | ✗ | ✓ | ✓ |
| PeakRDL | Free | ✗ | ✓ | ✗ | ✗ | ✓ | ✓ |
| Cheby | Free | ✓ | Partial | ✗ | ✗ | ✓ | ✓ |
Axion-HDL
Axion-HDL is a free, open-source AXI4-Lite register generator that's been steadily closing feature gaps since its first release. As of v1.2.0 it supports the full round-trip in both VHDL and SystemVerilog: you can annotate signals in a .vhd or .sv source file and generate register interfaces in either language — or both at once.
The annotation workflow is the main differentiator. Instead of maintaining a separate config file, you tag signals directly in your HDL with inline @axion comments. The tool reads the source, extracts the register map, and generates everything else.
-- VHDL annotation syntax:
signal ctrl : std_logic_vector(31 downto 0); -- @axion RW W_STROBE DESC="Control"
signal status : std_logic_vector(31 downto 0); -- @axion RO DESC="Status"
// SystemVerilog annotation syntax (identical):
logic [31:0] ctrl; // @axion RW W_STROBE DESC="Control"
logic [31:0] status; // @axion RO DESC="Status"Pros
- HDL annotations: VHDL and SystemVerilog inline
@axioncomments — no separate config file needed - Multi-format input:
.vhd,.sv, YAML, XML, JSON, TOML, mix freely - Dual HDL output: generate VHDL and SystemVerilog from the same source in one run
- Built-in CDC: configurable 2/3/4-stage synchronizers, per register
- Write/read strobes: one-cycle pulses on register access
- Wide signal splitting: 64-bit+ signals automatically spread across addresses
- Subregisters: pack multiple bit fields into one address
- Three interfaces: CLI, Python API, Web GUI — all free
- Rule check: validate your register map before generating
- 100% free: MIT license, no paid tiers
Cons
- No UVM register model generation
- No SystemRDL input support
- Newer tool, smaller community than hdl-registers or PeakRDL
Best for: Teams working in VHDL or SystemVerilog who want annotation-based register generation, built-in CDC, and a GUI — all without paying for anything.
airhdl
airhdl is a commercial, web-based register generator. It has a polished browser UI, supports both HDL output languages, and adds collaboration and versioning features aimed at teams. The CLI tool requires a Pro subscription.
Pros
- Polished web interface
- VHDL and SystemVerilog output
- Built-in design rule checking
- Team collaboration and version history (Pro)
- Good documentation and support
Cons
- $199/year for full features and CLI access
- Closed source — vendor lock-in risk
- Data lives on external servers
- No inline HDL annotation support
- No built-in CDC generation
Best for: Teams with budget who want a supported commercial product with a polished UI and collaboration features.
hdl-registers
hdl-registers is a mature, production-tested open-source generator. It's fast, has an extensive Python API, and is used in real production designs. If you're comfortable with CLI-only tools and TOML config files, it's hard to fault.
Pros
- Extremely fast — generation in ~10 ms
- VHDL and SystemVerilog output
- C++, Python, HTML output formats
- Well-documented Python API
- Mature and production-tested
Cons
- No GUI
- TOML/YAML/JSON config files required — no HDL annotation support
- No built-in CDC generation
- Steeper learning curve
Best for: Experienced developers who want maximum speed, a strong Python API, and are fine without a GUI.
vhdmmio
vhdmmio was developed at TU Delft and generates VHDL from YAML. It hasn't been updated since 2019 and is still labeled "alpha" in its own README.
Pros
- Clean YAML syntax
- Vendor-agnostic VHDL output
- Simple pip install
Cons
- Abandoned — last release September 2019
- Still "alpha" per its own README
- No SystemVerilog output
- No GUI
- No CDC support
⚠ Maintenance warning
vhdmmio has had no commits in over six years. It may work for simple cases but we'd recommend choosing an actively maintained tool for any new project.
RgGen
RgGen is a Ruby-based register generator with broad input format support, including SystemRDL and Excel spreadsheets. Its plugin architecture makes it highly extensible, and it's one of the few free tools that generates UVM register models.
Pros
- Many input formats: YAML, JSON, TOML, xlsx, SystemRDL
- VHDL and SystemVerilog output
- UVM register model generation
- Plugin system for customization
- Active development
Cons
- Requires Ruby — unusual dependency in HDL environments
- Slower generation (~10 seconds)
- No GUI
- No built-in CDC generation
- Complex configuration for advanced features
Best for: Teams who need UVM RAL generation or SystemRDL/spreadsheet input, and are comfortable with Ruby.
PeakRDL
PeakRDL is built around the SystemRDL 2.0 standard — an Accellera industry-standard register description language. It's the go-to choice for teams that need strict IP-XACT compliance or UVM register models.
Pros
- SystemRDL 2.0 compliant
- IP-XACT import and export
- Rich HTML documentation
- UVM register model generation
- Extensible plugin architecture
Cons
- No VHDL output — SystemVerilog only
- Requires learning SystemRDL syntax
- No GUI
- No built-in CDC generation
Best for: SystemVerilog teams that need SystemRDL or IP-XACT compliance, or UVM register model generation.
Cheby (CERN)
Cheby is developed at CERN and used in physics experiments. It's notable for supporting both AXI4 and Wishbone buses from the same YAML source.
Pros
- Battle-tested at CERN
- Supports Wishbone and AXI4
- Hierarchical register maps
- Backward-compatible with wbgen
Cons
- Limited documentation outside of CERN context
- YAML-only input
- No GUI
- Niche community
- Partial SystemVerilog output
Best for: Projects requiring Wishbone support, or teams in physics/research communities already using wbgen.
Detailed feature tables
Input format support
| Tool | YAML | JSON | XML | TOML | VHDL annot. | SV annot. | SystemRDL | Spreadsheet |
|---|---|---|---|---|---|---|---|---|
| Axion-HDL | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✗ | ✗ |
| airhdl | ✗ | ✓ | ✗ | ✗ | ✗ | ✗ | ✗ | ✗ |
| hdl-registers | ✓ | ✓ | ✗ | ✓ | ✗ | ✗ | ✗ | ✗ |
| vhdmmio | ✓ | ✗ | ✗ | ✗ | ✗ | ✗ | ✗ | ✗ |
| RgGen | ✓ | ✓ | ✗ | ✓ | ✗ | ✗ | ✓ | ✓ |
| PeakRDL | ✗ | ✗ | ✓ (IP-XACT) | ✗ | ✗ | ✗ | ✓ | ✗ |
| Cheby | ✓ | ✗ | ✗ | ✗ | ✗ | ✗ | ✗ | ✗ |
Output format support
| Tool | VHDL | SystemVerilog | C Header | HTML Docs | IP-XACT | YAML/JSON out | UVM RAL |
|---|---|---|---|---|---|---|---|
| Axion-HDL | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✗ |
| airhdl | ✓ | ✓ | ✓ | ✓ | ✗ | ✗ | ✗ |
| hdl-registers | ✓ | ✓ | ✓ | ✓ | ✗ | ✗ | ✗ |
| vhdmmio | ✓ | ✗ | ✓ | ✓ | ✗ | ✗ | ✗ |
| RgGen | ✓ | ✓ | ✓ | ✗ | ✗ | ✗ | ✓ |
| PeakRDL | ✗ | ✓ | ✓ | ✓ | ✓ | ✗ | ✓ |
| Cheby | ✓ | Partial | ✓ | ✓ | ✗ | ✗ | ✗ |
Advanced features
| Tool | Built-in CDC | Subregisters | Wide signals | R/W strobes | Rule check | Web GUI | Python API |
|---|---|---|---|---|---|---|---|
| Axion-HDL | ✓ 2–4 stage | ✓ | ✓ | ✓ | ✓ | ✓ Free | ✓ |
| airhdl | ✗ | ✓ | ✓ | ✓ | ✓ | ✓ Paid | ✗ |
| hdl-registers | ✗ | ✓ | ✓ | Partial | ✗ | ✗ | ✓ |
| vhdmmio | ✗ | ✓ | Partial | Partial | ✗ | ✗ | ✗ |
| RgGen | ✗ | ✓ | ✓ | ✓ | ✗ | ✗ | ✗ |
| PeakRDL | ✗ | ✓ | ✓ | ✓ | ✗ | ✗ | ✓ |
| Cheby | ✗ | ✓ | Partial | ✗ | ✗ | ✗ | ✗ |
Which should you choose?
Choose Axion-HDL if:
- You work in VHDL or SystemVerilog and want to annotate registers directly in your source
- You need built-in CDC synchronizers without writing them by hand
- You want VHDL and SystemVerilog output from the same source in one command
- You want a GUI without paying for it
- You want an all-in-one solution (CLI + Python API + GUI) that's MIT licensed
Choose airhdl if:
- You have budget for $199/year and want a polished, commercially supported product
- You need team collaboration features and version history
- A browser-based workflow suits your team
Choose hdl-registers if:
- You need maximum generation speed and a strong Python API
- You're comfortable with CLI-only tools
- You need both VHDL and SystemVerilog from a mature, production-tested tool
Choose RgGen if:
- You need UVM register model generation for free
- Your input source is a spreadsheet or SystemRDL
- You're already in a Ruby environment
Choose PeakRDL if:
- You work exclusively in SystemVerilog (no VHDL needed)
- Your flow requires SystemRDL 2.0 or strict IP-XACT compliance
- You need UVM register model generation
Choose Cheby if:
- Your design uses Wishbone alongside or instead of AXI4
- You're in a physics/research environment already using wbgen
Bottom line
For pure VHDL teams, the choice used to be straightforward: Axion-HDL if you wanted annotations and a GUI, hdl-registers if you wanted speed and maturity. Now that Axion-HDL has SystemVerilog support on both input and output, the gap with the competition has narrowed significantly — and it's still free.
If you're starting a new project today and don't have a compelling reason to pay for airhdl or adopt SystemRDL, Axion-HDL or hdl-registers cover the vast majority of real-world register automation needs.